Chip Design: Electronic Design Automation

A small, undetected design defect or conflict in one system block can translate into system failure in the integrated system, creating a risk to product safety and customer satisfaction. As design complexity increases, it is becoming more and more difficult to test for errors and functional failure. Finding these defects is a difficult task but recent Formal Verification methodologies have proved very successful. Satalia increases the speed, throughput and reliability of the algorithms that Formal Verification depends on.

The Satalia SolveEngine reduces business risks that could impact product safety, time to market and customer satisfaction by finding hard to spot, yet critical defects before they enter the field. We also reduce development risks with automated testing to analyze all of the possible paths to a block defect across the entire design.

Detail

Chip Design has a huge pain caused by the increase in complexity of designs. As chip designs become more complex, it is becoming exponentially more difficult to test them for defects. Traditional verification techniques often fail to discover critical defects. As a consequence, over the past few years, the industry has adopted methods that rely heavily on optimization algorithms to identify design defects. Optimization algorithms are therefore now very important to the design and it is common for verification processes to be hindered by the performance of the algorithms.

Formal Verification

There are broadly two techniques for testing system designs: Simulation and Formal Verification. Simulation is the traditional technique for testing that a system produces the desired behaviour. However, a major limitation of Simulation is that while it can demonstrate the presence of defects, it cannot demonstrate a system is defect-free. Additionally, as the scale and complexity of systems grow it is computationally impossible to exhaustively verify a system through Simulation. The alternative is Formal Verification. The Formal Verification process uses optimization algorithms to exhaustively prove the behaviour of a chip design.

While many have routinely hosted Formal Verification experts since the early '90s, the performance of the underlining algorithms to support this type of analysis were not sufficient to use as a routine part of the design process. However, over the past decade there has been rapid progress on particular classes of optimization algorithms that are critical to Formal Verification methods. Even though there are high intellectual barriers to adoption their success has been responsible for the growth of the use of Formal Verification methods in the system design industry. It is now estimated that 25% of the defects in chip designs can only be found using Formal Verification rather than simulation.

Formal Verification tools are developed both internally in large companies and purchased from third party vendors. A formal verification tool generally consists of several different components including the choice of system abstraction, propriety languages and choice of algorithms. Additionally, care must be taken in managing and maintaining compute infrastructure to guarantee algorithms run fast. Despite recent successes there are still many challenges facing companies that require or offer formal verification solutions. In particular, the increase in scale and complexity of verification problems produces several problems.

Substantial effort from highly skilled verification engineers (both in-house and often by external consultants) is required to 'persuade' a few percent of these difficult problems to solve. The significant percentage of problems that fail to solve mean that parts of a systems behaviour remains unknown - a great risk. It is estimated that on certain projects 3+ months of simulation time is used to solve just the few (formally) unsolvable problems.

Even marginal improvements in optimization can help system engineers to significantly improve the design process by uncovering more critical defects early. There are several business and technological challenges facing formal verification tools:

• how to increase algorithm performance

• how to better stay abreast of developments in academic research

• how to amortize the cost of compute resources

Companies are desperately trying to respond by:

• building costly R&D teams

• creating tenuous and ad-hoc links with academia to license IP, and

• spending more money to increase compute resource

Formal Verification Partners

Formal Verification software are developed both internally in large companies and purchased from third party vendors. This software generally consists of several different components including the choice of system abstraction, propriety languages and choice of algorithms. The algorithms have tended to be researched and developed on a product-by-product basis or acquired through ad-hoc licence agreements with public research institutions. Existing software has been limited to rely heavily on embedded local libraries, and the onus placed on the design engineer to choose the appropriate algorithm for a particular problem.

The nature of these algorithms means that they are very compute intensive. Satalia works with formal verification partners to:

• develop and maintain its design tool and engineering user base, including methods for improving integration in existing work flows

• update and extend its algorithm portfolio

• develop and maintain compute infrastructure